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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Highest voted questions in CO and Architecture

#1
47.5k
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4 answers
142 votes
GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages:IF – instruction fetch from instruction memoryRD – Instruction decode and register readEX – Execute: ...
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#2
65.0k
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19 answers
129 votes
GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An avera...
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#3
23.2k
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10 answers
127 votes
GATE CSE 2014 Set 1 | Question: 44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses ...
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#4
24.7k
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9 answers
103 votes
GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...
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#5
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12 answers
100 votes
GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...
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#6
34.9k
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8 answers
98 votes
GATE CSE 2005 | Question: 65
Consider a three word machine instruction$\text{ADD} A[R_0], @B$The first operand (destination) $“A[R_0]”$ uses indexed addressing mode with $R_0$ as the index regist...
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#7
49.0k
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10 answers
97 votes
GATE CSE 2013 | Question: 45
Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (...
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#8
33.1k
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10 answers
93 votes
GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...
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#9
39.2k
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9 answers
91 votes
GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...
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#10
27.1k
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4 answers
81 votes
GATE CSE 2015 Set 2 | Question: 44
Consider the sequence of machine instruction given below:$$\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7,...
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#11
21.4k
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5 answers
81 votes
GATE CSE 2014 Set 2 | Question: 43
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?A...
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#12
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8 answers
80 votes
GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
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#13
30.4k
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5 answers
78 votes
GATE CSE 2017 Set 2 | Question: 45
The read access times and the hit ratios for different caches in a memory hierarchy are as given below:$$\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access ...
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#14
19.5k
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8 answers
76 votes
GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac...
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#15
26.6k
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8 answers
74 votes
GATE CSE 2010 | Question: 49
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...
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#16
26.0k
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8 answers
73 votes
GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equiva...
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#17
14.5k
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5 answers
73 votes
GATE CSE 2013 | Question: 20
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. ...
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#18
18.0k
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8 answers
71 votes
GATE CSE 2000 | Question: 12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the ins...
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#19
41.8k
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5 answers
70 votes
GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...
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#20
29.5k
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4 answers
70 votes
GATE CSE 2004 | Question: 63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $$\begin{array}{|l|l|c|} \hline \text {Instruction} & \t...
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