Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} & \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...

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BARC 2024 CSE
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Made Easy Class Question.
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sanjeet24 asked Mar 5

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Gate 2024 CS/IT shift-2 Question 61
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#Self doubt COA

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GATE CSE 2024 | Set 2 | Question: 1
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GATE CSE 2024 | Set 2 | Question: 21
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GATE CSE 2024 | Set 2 | Question: 47
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GATE CSE 2024 | Set 2 | Question: 48
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GATE CSE 2024 | Set 2 | Question: 51
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GATE CSE 2024 | Set 1 | Question: 5
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Arjun asked Feb 16

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GATE CSE 2024 | Set 1 | Question: 20
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Arjun asked Feb 16

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GATE CSE 2024 | Set 1 | Question: 43
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Arjun

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GATE CSE 2024 | Set 1 | Question: 45
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Arjun

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Arjun asked Feb 16

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#pipeline#coa#mocktest

Mohanasainarala

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Mohanasainarala asked Feb 4

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