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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2}  & \textbf{2023}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2&1&2&3&1&2&3
\\\hline\textbf{2 Marks Count} & 2&2&2&2&2&2&2&2&2
\\\hline\textbf{Total Marks} & 6&6&6&5&6&7&\bf{5}&\bf{6}&\bf{7}\\\hline
\end{array}}}$$

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Highest voted questions in Digital Logic

#1
52.8k
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20 answers
114 votes
GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this ...
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#2
62.9k
views
12 answers
100 votes
GATE CSE 2015 Set 2 | Question: 48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that o...
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#3
27.7k
views
8 answers
94 votes
GATE CSE 2015 Set 1 | Question: 39
Consider the operations$\textit{f (X, Y, Z) = X'YZ + XY' + Y'Z'}$ and $\textit{g (X, Y, Z) = X'YZ + X'YZ' + XY}$Which one of the following is correct?Both $\left\{\textit...
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#4
21.0k
views
7 answers
91 votes
GATE CSE 2006 | Question: 40
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray...
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#5
31.4k
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9 answers
85 votes
GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is$\Theta (1)$$\...
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#6
37.3k
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8 answers
80 votes
GATE CSE 2015 Set 2 | Question: 7
The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.
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#7
33.6k
views
17 answers
80 votes
GATE CSE 2004 | Question: 62
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both com...
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#8
19.0k
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5 answers
71 votes
GATE CSE 2006 | Question: 8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following...
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#9
15.2k
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3 answers
70 votes
GATE CSE 1994 | Question: 3.3
State True or False with one line explanationA FSM (Finite State Machine) can be designed to add two integers of any arbitrary length (arbitrary number of digits).
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#10
15.4k
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6 answers
70 votes
GATE CSE 2006 | Question: 36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers ...
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#11
19.7k
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7 answers
69 votes
GATE CSE 2016 Set 2 | Question: 07
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value o...
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#12
31.9k
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9 answers
69 votes
GATE CSE 2007 | Question: 34
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer neede...
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#13
82.9k
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4 answers
68 votes
Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OREx-NorHalf AdderHalf SubtractorFull AdderFull SubtractorNAND??????NOR??????
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#14
19.8k
views
6 answers
66 votes
GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):$$\small {\begin{array}{|c|c|c|c|l|}\hline\textbf{Clear}& ...
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#15
16.9k
views
9 answers
65 votes
GATE CSE 2017 Set 1 | Question: 7
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this repres...
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#16
18.3k
views
9 answers
65 votes
GATE CSE 2003 | Question: 43
The following is a scheme for floating point number representation using $16$ bits.Let $s, e,$ and $m$ be the numbers represented in binary in the sign, exponent, and man...
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#17
21.3k
views
4 answers
62 votes
GATE CSE 2006 | Question: 38
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors...
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#18
21.8k
views
5 answers
62 votes
GATE CSE 2001 | Question: 2.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$Co...
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#19
16.5k
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6 answers
60 votes
GATE CSE 2003 | Question: 47
Consider the following circuit composed of XOR gates and non-inverting buffers.The non-inverting buffers have delays $\delta_1 = 2 ns$ and $\delta_2 = 4 ns$ as shown in t...
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#20
17.3k
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3 answers
60 votes
GATE CSE 2005 | Question: 62
Consider the following circuit involving a positive edge triggered D FF.Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line $A$ in t...
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