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Recent questions tagged adder

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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders:$$\begin{aligned}& \mathrm{f}_1=A \oplus B \oplus C \\& \mathrm{f}_2=A^{\prime} B C+A B^{\prime} ...
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...
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Digital Logic | Sample question
The number of full and half-adders required to add $32$-bit numbers is______________________
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Made Easy Test Series Mock Test
How to calculate the third option?
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DRDO CSE 2022 Paper 1 | Question: 24
Given a truth table of the full adder for three inputs. Draw a full adder circuit with a decoder and two $\text{OR}$ gates.$$\begin{array}{|c|c|c|c|c|}\hline \mathrm{X} &...
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Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 tim...
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GO Classes Test Series 2023 | Digital Logic | Test 2 | Question: 17
If $A$ and $B$ are the inputs to a half adder, a half subtractor. $X$ and $Y$ are the Sum and Difference and $\mathrm{C}$ is a Carry of a Half adder and $D$ is a borrow o...
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NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated?Half adderFull adderParallel adderCarry-look ahead adder
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NIELIT 2016 DEC Scientist B (IT) - Section B: 33
How many inputs are required in Full Adder Circuit?$2$$3$More than two inputsNone of the above
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UGC NET CSE | December 2005 | Part 2 | Question: 7
A half-adder is also known as :$\text{AND}$ Circuit$\text{NAND}$ Circuit$\text{NOR}$ Circuit$\text{EX-OR}$ Circuit
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ISRO2020-9
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time...
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Morris Mano Edition 3 Exercise 5 Question 12 (Page No. 199)
It is necessary to design a decimal Adder for two digits represented in Excess-3 code. Show that the correction after adding the two digits with a four-bit binary adder i...
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Morris Mano Edition 3 Exercise 5 Question 11 (Page No. 198)
Construct a 4-digit BCD adder-subtractor using 4 BCD adders. Use the Block diagram for each component, showing only inputs and outputs.
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Morris Mano Edition 3 Exercise 5 Question 9 (Page No. 198)
How many Unused Combinations are there in BCD adder?
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Morris Mano Edition 3 Exercise 5 Question 8 (Page No. 198)
Derive the two-level Boolean expression for the output carry $C _5$ shown in the look-ahead carry generator of the figure
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Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time...
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Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows:$P _i = A _i + B _ i$$G _i = A _iB _i$Show that the output carry and output sum of a full adder becomes$C _...
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Morris Mano Edition 3 Exercise 5 Question 5 (Page No. 198)
Using the AND-OR-Invert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i’P _i + G _i...
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Morris Mano Edition 3 Exercise 5 Question 4 (Page No. 197)
The adder-subtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S...
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Morris Mano Edition 3 Exercise 5 Question 3 (Page No. 197)
The adder-subtractor of the figure is used to subtract the following unsigned 4-bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the ci...
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Morris Mano Edition 3 Exercise 5 Question 2 (Page No. 197)
Construct a BCD-to-Excess-3-code converter with a 4-bit adder.remember that the Excess-3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be don...
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Morris Mano Edition 3 Exercise 5 Question 1 (Page No. 197)
Construct a 16-bit parallel adder with four MSI circuits, each containing a four-bit parallel adder. Use a block diagram with 9 inputs and five outputs for each 4-bit add...
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GATE Overflow | Mock GATE | Test 1 | Question: 14
Let $S(x,y,z)$ and $C(x,y,z)$ represents the Sum & Carry function of a full adder circuit. Which of the following options best represents $S(x,y,z)$ and $C(x,y,z)$ respec...
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Full adder
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MadeEasy Workbook: Digital Logic - Adder
x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d...
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