Recent questions and answers in CO and Architecture / GATE Overflow for GATE CSE

36 votes

5 answers

1

GATE CSE 1999 | Question: 2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic

The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typicallyhas fewer instructionshas fewer addressing modeshas more registersis easi...

Swarup kotal

9.1k views

Swarup kotal answered 1 day ago

19 votes

5 answers

2

GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________

Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $3...

Bhaiyasaheb

7.4k views

Bhaiyasaheb answered 6 days ago

3 votes

5 answers

3

GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\t...

Bhaiyasaheb

5.5k views

Bhaiyasaheb answered 6 days ago

0 votes

3 answers

4

GATE CSE 2024 | Set 1 | Question: 5
Which one of the following statements is FALSE? In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle For bulk data transfer, the burst mode of ... driven I/O mechanism The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Which one of the following statements is FALSE?In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a s...

Pranav Redij

2.2k views

Pranav Redij answered Apr 28

0 votes

0 answers

5

COA : Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information ... 12 bits address field. The size of the control memory required is? I am not able to solve this question please help

Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...

ENTJ007

92 views

ENTJ007 asked Apr 18

97 votes

10 answers

6

GATE CSE 2013 | Question: 45
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (...

Sun Wukong

48.4k views

Sun Wukong answered Apr 17

1 votes

2 answers

7

Control Unit
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Each micro instruction contains 3 fields: 118 control signals to support horizontal control unit, a MUX select field to select one of 8 inputs, and a next address field. The size of control memory needed is?

Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Eac...

Psy Duck

270 views

Psy Duck answered Apr 5

0 votes

3 answers

8

GATE CSE 2024 | Set 1 | Question: 45
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time can be fully parallelized. The overhead for using an ... the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is __________.

The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time ...

shivom

1.9k views

shivom answered Apr 1

0 votes

0 answers

9

Data Representation and Arithmetic Algorithms
MULTIPLICATION OF (-15) AND (3) USING BOOTH'S ALGORITHM Please solve this question😭

MULTIPLICATION OF (-15) AND (3) USING BOOTH'S ALGORITHMPlease solve this question😭

Siddhi Jagtap

81 views

Siddhi Jagtap asked Apr 1

0 votes

1 answer

10

BARC 2024 CSE
How many 256 X 1K bit chips are required to build 1 MB of memory?

How many 256 X 1K bit chips are required to build 1 MB of memory?

mrtejas99

165 views

mrtejas99 answered Mar 18

0 votes

0 answers

11

Made Easy Class Question.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below. S1 S2 S3 S4 I1 1 3 1 2 I2 1 1 3 1 I3 2 1 1 2 I4 1 1 1 2 (a) How many cycles are required to complete the ... ;= n; i++) { I1; I2; I3; I4; } The output of the instruction "I2" will be available after _____ cycles for I2.

Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below.S1S2S3S4I11312I21131I32112I41112...

sanjeet24

183 views

sanjeet24 asked Mar 5

52 votes

10 answers

12

GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below:$$\begin{array}{|...

sanjeet24

35.0k views

sanjeet24 answered Mar 4

1 votes

1 answer

13

GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$ ... the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.

A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instruc...

Suraj7

1.9k views

Suraj7 answered Feb 21

0 votes

0 answers

14

Gate 2024 CS/IT shift-2 Question 61
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. ... the number of bits used to encode the immediate value/address field. The value of 𝑋 + 2𝑌 + 𝑍 is ________

A processor uses a 32-bit instruction format and supports byte-addressable memoryaccess. The ISA of the processor has 150 distinct instructions. The instructions areequal...

Omkar_Naikwadi

225 views

Omkar_Naikwadi asked Feb 19

2 votes

1 answer

15

GATE CSE 2024 | Set 2 | Question: 47
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a $16$-bit scalar field. If $8$ addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.

A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two regi...

amanbh123

1.8k views

amanbh123 answered Feb 18

2 votes

2 answers

16

GATE CSE 2024 | Set 1 | Question: 20
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are ... cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Whic...

Deepak Poonia

4.2k views

Deepak Poonia answered Feb 18

1 votes

2 answers

17

GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$ miss rate on instruction cache and $8 \%$ miss rate on data ... rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is __________.

A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$...

Deepak Poonia

2.8k views

Deepak Poonia answered Feb 17

2 votes

2 answers

18

GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block ... write miss in $\text{WTC}$ always writes the victim cache block to main memory before loading the missed block to the cache

Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy...

Sachin Mittal 1

2.3k views

Sachin Mittal 1 answered Feb 17

1 votes

1 answer

19

GATE CSE 2024 | Set 2 | Question: 1
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per ... $\text{DMA}$? $2,56,000$ $3,200$ $25,60,000$ $32,000$

Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle...

JayRathi

2.5k views

JayRathi answered Feb 17

1 votes

1 answer

20

GATE CSE 2024 | Set 2 | Question: 21
An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequence of instructions to be executed in a pipelined processor: $\text{I 1: DIV R3, R1, R2}$ ... $\text{I 3}$ There is a WAW dependency on $\text{R 3}$ between $\text{I 3}$ and $\text{I 4}$

An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequenc...

Deepak Poonia

2.0k views

Deepak Poonia answered Feb 16

0 votes

0 answers

21

#Self doubt COA

Çșȇ ʛấẗẻ

328 views

Çșȇ ʛấẗẻ asked Feb 16

2 votes

0 answers

22

GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is then redesigned to operate on a $5$ ... hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ____________.

A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is the...

Arjun

1.9k views

Arjun asked Feb 16

4 votes

1 answer

23

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped? Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data except for the array x are stored in registers, and that the ... ) { sum += x[i]; } What is the miss rate for the above loop? (roundoff to two decimal places)

Consider the cache of size 512 bytes that is direct-mapped?Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data...

GO Classes

467 views

GO Classes answered Feb 5

5 votes

1 answer

24

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 62
At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can be listed in [track:sector] form as follows: ... Shortest Seek Time First Scan (initially moving upwards) Look (initially moving upwards) C-SCAN (initially moving upwards)

At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can be listed in [track:secto...

GO Classes

469 views

GO Classes answered Feb 5

11 votes

1 answer

25

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 63
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a 4-stage pipeline where branch target locations ... $1.38$ For both "predict taken", "predict not taken" branch predictions, CPI is the $1.30$

Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a...

GO Classes

798 views

GO Classes answered Feb 5

7 votes

3 answers

26

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 48
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to encode one register number, $6$ bits ... $4$ bytes long. How many instructions away (the number of instructions) from the $\textsf{BEQ}$ instruction could we reach?

Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to e...

Kushagrakk

694 views

Kushagrakk answered Feb 4

0 votes

0 answers

27

#pipeline#coa#mocktest

Mohanasainarala

99 views

Mohanasainarala asked Feb 4

25 votes

4 answers

28

GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...

ajayraho

16.7k views

ajayraho answered Jan 31

9 votes

2 answers

29

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 53
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$ $\textsf{0x80000004}$ $\textsf{0x80000008}$ $\textsf{0x80000010}$ $\textsf{0x80000002}$

Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$$...

Sachin Mittal 1

875 views

Sachin Mittal 1 answered Jan 29

64 votes

3 answers

30

GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction

Delayed branching can help in the handling of control hazardsFor all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or f...

Deepak Poonia

18.1k views

Deepak Poonia answered Jan 28

7 votes

1 answer

31

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 35
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in which $30 \%$ of the instructions are ... is always started and ignored if the branch is taken. What is the throughput (Million instructions per second) of the system?

Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in whic...

Aparichit0

716 views

Aparichit0 answered Jan 28

2 votes

1 answer

32

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 34
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false? Instruction immediately following the branch condition Instruction immediately preceding the branch condition Instruction that belongs to a different a subroutine It waits till the branch condition is evaluated

In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false?Instruction immediately following the branch ...

GO Classes

463 views

GO Classes answered Jan 28

6 votes

1 answer

33

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties: The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes) The cache uses an LRU (least recently used) policy for eviction. The cache is initially empty. Suppose that for the following ... cache? $\text{B}=4$ bytes $\text{B}=8$ bytes $\text{B}=16$ bytes None of the above.

Assume a cache memory with the following properties:The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes)The cache uses an LRU (least recently used) policy...

GO Classes

787 views

GO Classes answered Jan 28

5 votes

1 answer

34

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 58
Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$), assuming $\mathrm{M}$ is $32$ bits wide? shift $\text{M}$ right by $4,$ ... $0000000 \mathrm{Fh}$, save the result, shift result left by $2,$ and add the saved result to current result.

Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$), assuming $\mathrm{M}$ is $32...

GO Classes

446 views

GO Classes answered Jan 28

1 votes

3 answers

35

MADE EASY TEST SERIES 2024 #COA
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ADD operation with Address 1 used as Source1 and Destination, Address2 used ... operation consumes 4 cycles. Memory reference consumes 6 cycles. Time required to complete the instruction is in (ns).

Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ...

vedantk

480 views

vedantk answered Jan 27

3 votes

2 answers

36

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?

Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresse...

prasantkr.singh

547 views

prasantkr.singh answered Jan 23

6 votes

1 answer

37

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 20
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI on machine $\text{A}$ is $1.2.$ For the same program, the average ... Machine $\text{B}$, with respect to this program. What is $\mathrm{K}?$ $1$ $4 / 3$ $2$ $3 / 4$

The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI ...

GO Classes

720 views

GO Classes answered Jan 21

7 votes

1 answer

38

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 49
Consider the following code fragment: Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true data dependencies be $\mathrm{X}$ ... output dependencies be $\text{Z}$. What is $\mathrm{X}+2 \mathrm{Y}+3 \mathrm{Z}?$

Consider the following code fragment:Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true d...

GO Classes

1.1k views

GO Classes answered Jan 21

8 votes

1 answer

39

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits. Which of the following address pairs can be placed in the cache simultaneously? $\textsf{3AC6 F45 6}$ ... $\textsf{5E3C 768 0}$ and $\textsf{8F3C 768 A}$ $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$

A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits.Which of the following address pairs...

GO Classes

898 views

GO Classes answered Jan 21

55 votes

2 answers

40

GATE CSE 2008 | Question: 36
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III

Which of the following are NOT true in a pipelined processor?Bypassing can handle all RAW hazardsRegister renaming can eliminate all register carried WAR hazardsControl h...

prasantkr.singh

22.2k views

prasantkr.singh answered Jan 19

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