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Recent questions tagged machine-instruction

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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 20
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI on machine $\text{A}$ is $1.2.$ For the same program, the average ... Machine $\text{B}$, with respect to this program. What is $\mathrm{K}?$ $1$ $4 / 3$ $2$ $3 / 4$
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI ...
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#Applied Course
How I2-I4 is counted?
How I2-I4 is counted?
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Co Arcitecture
A CPU has instructions 12 bits long. The size of an address field is 4 bits. It is possible to have: 14 commands of two addresses 29 commands of an address 48 zero-address instructions. using this command form?
A CPU has instructions 12 bits long. The size of an address field is 4 bits. It is possible to have: 14 commands of two addresses 29 commands of an address 48 zero-addres...
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GATE CSE 2023 | Question: 31
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. Which one of ... $(3,4,4, \text{L01)}$ $(8,1,1, \text{L02)}$ $(3,1,1, \text{L01)}$
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics...
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Unacademy Practice Question
Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and write operations as 30% and 40% respectively. The tine taken by ... 50% read requests and 50% write requests. What is the average memory access time considering both read and write operations ?
Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and...
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Practice Question Unacademy - Vishvadeep Gothi
Consider a system that supports 2-address, 1-address, and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address instructions and 'y' 1-address instructions then which of the following is the maximum ... $2 ^ i - 2 ^ a * x - y * 2 ^ a$
Consider a system that supports 2-address, 1-address, and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address ...
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CO and Arcitecture | RISC | Instruction pipelining
MSQ Which among the following statements is/are TRUE for a pipelined RISC computer. PC is usually incremented during Instruction Cycle (IF,ID) PC may be incremented during Execution Cycle (EX,MA,WB) Filling the Accumulator ... during the Instruction Cycle (IF,ID) All non-register memory fetching operations are done in Load instructions only.
MSQWhich among the following statements is/are TRUE for a pipelined RISC computer.PC is usually incremented during Instruction Cycle (IF,ID)PC may be incremented during ...
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SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
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4 Address Instruction
Where are 4 Address Instructions are used and how?
Where are 4 Address Instructions are used and how?
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How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?
The instruction format is CMP R1, R2.How will the carry and zero flags we be modified after above instruction is executed? Case 1:R1< R2 Carry Flag = 1 Zero Flag = 0R1= R...
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GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... . Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the m...
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UGC NET CSE | October 2020 | Part 2 | Question: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
Arrange the following types of machine in descending order of complexity.SISDMIMDSIMDChoose the correct answer from the options given below:$a,b,c$$c,b,a$$b.c.a$$c,a,b$
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NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
An instruction used to set the carry flag in a computer can be classified asdata transferprocess controllogicalprogram control
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NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii
Match list $I$ with List $II$ and select the correct answer using the codes given below the lists :$${\begin{array}{|c|c|c|}\hline&\textbf{List I} & & \textbf{List II}\\\...
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NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $...
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NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii
Match list $I$ with List $II$ and select the correct answer using the codes given below the lists.$${\begin{array}{|c|c|c|}\hline&\textbf{List I} & & \textbf{List II}\\\h...
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NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
MIMD stands forMultiple Instruction Multiple DataMultiple Instruction Memory DataMemory Instruction Multiple dataMultiple Information Memory data
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UGC NET CSE | January 2017 | Part 2 | Question: 32
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$
Consider the following assembly language instructions:mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0What is the value in $ax$ register after ...
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UGC NET CSE | January 2017 | Part 2 | Question: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ ... $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and s...
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GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
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ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ different implementations of the fo...
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 32 (Page No. 176)
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.
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