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Recent questions tagged cisc-risc-architecture

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GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
Consider the following processor design characteristics:Register-to-register arithmetic operations onlyFixed-length instruction formatHardwired control unitWhich of the c...
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Test by Bikram | Mock GATE | Test 4 | Question: 28
There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction). Which of the following actions would improve the execution time of an arithmetically ... and the data cache without changing the clock cycle time. II only I and III III only I and II
There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction).Which of th...
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Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40
Show below are sements of a code run on a CISC and RISC archy separatelyCISC RISCMOV AX,05 ...
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GATE CSE 1999 | Question: 2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typicallyhas fewer instructionshas fewer addressing modeshas more registersis easi...
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