Recent questions tagged sequential-circuit / GATE Overflow for GATE CSE

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GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?

Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register us...

GO Classes

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GO Classes asked Feb 5

3 votes

1 answer

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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 25
A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its input, and continually outputs $\text{0's}$ until it sees the substring $011,$ ... Arrow $1 - (0/0)$ Arrow $3 - (1/0)$ Arrow $4 - (1/0)$ Arrow $5 - (1/1)$

A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its inp...

GO Classes

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GO Classes asked Jan 28

2 votes

3 answers

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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)

For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=01...

GO Classes

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GO Classes asked Jan 28

2 votes

1 answer

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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$

We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be:$\ma...

GO Classes

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GO Classes asked Jan 21

3 votes

1 answer

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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d

Consider the sequential circuit shown below.Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transiti...

GO Classes

726 views

GO Classes asked Jan 21

2 votes

2 answers

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GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

The circuit shown below is designed using two multiplexers.This circuit is equivalent to:a positive edge triggered $\mathrm{T}$ flip flopa negative edge triggered $\mathr...

GO Classes

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GO Classes asked Jan 13

0 votes

1 answer

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GATE CS Mock 2018 | Question 60 | GFG
Consider the following statements regarding counters: S1 : The Hamming distance of an Overbeck counter is $1$. and the Hamming distance of a Johnson counter is $2$. S2 : Only output sequence $0, 8, 12, 14, 15, 7, 3, 1, 0, ...$ is possible in Overbeck counter ... S3 are false and S1 is true (C) Only S1, S3 are false and S2 is true (D) All S1, S2, and S3 are true

Consider the following statements regarding counters:S1 : The Hamming distance of an Overbeck counter is $1$. and the Hamming distance of a Johnson counter is $2$.S2 : On...

rajveer43

176 views

rajveer43 asked Jan 12

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0 answers

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GFG CSE Mock 2018 | Sequential Circuits
Consider following counters: Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ... $0, 1, 2, 3, 5, 6, 0, ... $.

Consider following counters:Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ...

rajveer43

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rajveer43 asked Jan 12

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0 answers

9

A variation on Digital Logic: Morris Mano Edition 3 Exercise 7 Question 4 (Page No. 303)
Design a counter according to the state diagram above using only NAND gates and JK Flip-flops (if needed) complete with state tables

Design a counter according to the state diagram above using only NAND gates and JK Flip-flops (if needed) complete with state tables

Redcom1988

223 views

Redcom1988 asked Dec 23, 2023

0 votes

1 answer

10

made easy counters question

mudasirkhan

262 views

mudasirkhan asked Dec 15, 2023

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1 answer

11

madeeasy booklet
How to solve this?

How to solve this?

Sajal Mallick

292 views

Sajal Mallick asked Nov 20, 2023

0 votes

0 answers

12

madeeasy booklet
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is different.

Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is ...

Sajal Mallick

149 views

Sajal Mallick asked Nov 20, 2023

0 votes

0 answers

13

madeeasy ots digital logic
In the 2nd cycle as it is ripple counter Q0 will change and it will 0 so for that reason Q1 will not get clock and it will be in previous state that is 1. So output should be 01. Right??

In the 2nd cycle as it is ripple counter Q0 will change and it will 0 so for that reason Q1 will not get clock and it will be in previous state that is 1. So output shoul...

Sajal Mallick

231 views

Sajal Mallick asked Nov 19, 2023

1 votes

1 answer

14

GO Classes 2024 | IIITH Mock Test 5 | Question: 9
Two $\text{D}$ Flip flops are connected as a synchronous counter that goes through following sequence $ 00 \rightarrow 01 \rightarrow 11 \rightarrow 10 \rightarrow 00 $ Inputs $\text{D}_0$ and $\text{D}_1$ should be connected as$? ($Flip flop $\text{D}_1$ ... $\overline{\text{Q}}_0 \overline{\text{Q}}_1$ and $\text{Q}_0 \text{Q}_1$

Two $\text{D}$ Flip flops are connected as a synchronous counter that goes through following sequence$$00 \rightarrow 01 \rightarrow 11 \rightarrow 10 \rightarrow 00$$Inp...

GO Classes

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GO Classes asked Apr 30, 2023

1 votes

1 answer

15

GO Classes 2023 | IIITH Mock Test 1 | Question: 37
A new flip-flop, called AB flip-flop, is created as shown below. What does the flip-flop do? Set command when $A = 0 , B = 0$ Reset command when $A = 0 , B = 1$ Hold command when $A = 1 ,B = 0$ Toggle command when $A = 1 , B = 1$

A new flip-flop, called AB flip-flop, is created as shown below. What does the flip-flop do?Set command when $A = 0 , B = 0$Reset command when $A = 0 , B = 1$Hold command...

GO Classes

732 views

GO Classes asked Mar 26, 2023

1 votes

1 answer

16

GO Classes 2023 | IIITH Mock Test 1 | Question: 38
In an $SR$ latch created by cross-coupling two NOR gates, which of the following values for $S$ and $R$ will lead to an indeterminate state? $S = 0, R = 0$ $S = 0, R = 1$ $S = 1, R = 0$ $S = 1, R = 1$

In an $SR$ latch created by cross-coupling two NOR gates, which of the following values for $S$ and $R$ will lead to an indeterminate state?$S = 0, R = 0$$S = 0, R = 1$$S...

GO Classes

713 views

GO Classes asked Mar 26, 2023

2 votes

1 answer

17

GATE CSE 2023 | Memory Based Question: 22
The initial state of a given sequential circuit is $Q_0 Q_1 Q_2=011$. Which of the following state does not occur $101$ $111$ $001$ $100$

The initial state of a given sequential circuit is $Q_0 Q_1 Q_2=011$. Which of the following state does not occur$101$$111$$001$$100$

GO Classes

1.1k views

GO Classes asked Feb 5, 2023

0 votes

0 answers

18

A sequential circuit has two D flip-flops, two inputs x and y, and one output Z is specified by the following next-state and output equations A(t+1) = xy’ + x B B(t+1) = xA +xB’ Z = A (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.

M.Zain

651 views

M.Zain asked Dec 30, 2022

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